A three-dimensional (3D) Network-on-Chip (NoC) enables the design of highperformance and low power many-core chips. Existing 3D NoCs are inadequate formeeting the ever-increasing performance requirements of many-core processorssince they are simple extensions of regular 2D architectures and they do notfully exploit the advantages provided by 3D integration. Moreover, theanticipated performance gain of a 3D NoC-enabled many-core chip may becompromised due to the potential failures of through-silicon-vias (TSVs) thatare predominantly used as vertical interconnects in a 3D IC. To address theseproblems, we propose a machine-learning-inspired predictive design methodologyfor energy-efficient and reliable many-core architectures enabled by 3Dintegration. We demonstrate that a small-world network-based 3D NoC (3D SWNoC)performs significantly better than its 3D MESH-based counterparts. On average,the 3D SWNoC shows 35% energy-delay-product (EDP) improvement over 3D MESH forthe PARSEC and SPLASH2 benchmarks considered in this work. To improve thereliability of 3D NoC, we propose a computationally efficient spare-verticallink (sVL) allocation algorithm based on a state-space search formulation. Ourresults show that the proposed sVL allocation algorithm can significantlyimprove the reliability as well as the lifetime of 3D SWNoC.
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